1. Field of the Invention
The present invention relates to semiconductor packages and methods of fabricating the same, and, more particularly, to a wafer-level semiconductor package and a method of fabricating the same.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high electrical performance. Accordingly, wafer level packaging (WLP) technologies have been developed to meet the miniaturization requirement of semiconductor packages.
FIGS. 1A to 1D are schematic cross-sectional views showing a method of fabricating a wafer-level semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a thermal release tape 11 is formed on a carrier 10, and a plurality of semiconductor elements 12 are disposed on the thermal release tape 11. Each of the semiconductor elements 12 has an active surface 12a with a plurality of electrode pads 120 disposed thereon and a non-active surface 12b opposite to the active surface 12a. Each of the semiconductor elements 12 is disposed on the thermal release tape 11 through the active surface 12a thereof.
Referring to FIG. 1B, an encapsulant 15 is formed on the thermal release tape 11 by molding so as to encapsulate the semiconductor elements 12.
Referring to FIG. 1C, a curing process is performed to cure the encapsulant 15. Meanwhile, the thermal release tape 11 loses its adhesive property when being heated. As such, the thermal release tape 11 and the carrier 10 can be removed together to expose the active surfaces 12a of the semiconductor elements 12.
Referring to FIG. 1D, a Redistribution layer (RDL) process is performed such that an RDL structure 16 is formed on the encapsulant 15 and the active surfaces 12a of the semiconductor elements 12 for electrically connecting the electrode pads 120 of the semiconductor elements 12.
Then, an insulating layer 17 is formed on the RDL structure 16, and a plurality of openings are formed in the insulating layer 17 such that a portion of the RDL structure 16 is exposed for solder balls 18 to be mounted thereon.
However, the thermal release tape 11 easily expands when being heated during the molding process, thus easily causing positional deviations of the semiconductor elements 12 attached to the thermal release tape 11 (that is, the positions of the semiconductor elements 12 are deviated from the chip areas B), as shown in FIG. 1D′. The larger the size of the carrier 10 is, the greater the positional deviation of the semiconductor elements 12 becomes, thus adversely affecting the electrical connection between the RDL structure 16 and the semiconductor elements 12 and resulting in a low product yield.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.